Abstract
Aligned semiconducting carbon nanotubes are a potential alternative to silicon in the creation of scaled field-effect transistors (FETs) due to their easy miniaturization and high energy efficiency. However, it remains unclear whether aligned nanotube transistors can be fabricated at the same dimensions as low-node silicon technology and maintaining high performance. Here we report aligned carbon nanotube FETs that can be scaled to a size corresponding to the 10 nm silicon technology node. We first fabricate nanotube FETs with a contacted gate pitch of 175 nm (achieved by scaling the gate length and contact length to 85 nm and 80 nm, respectively) that exhibit an on current of 2.24 mA μm–1 and peak transconductance of 1.64 mS μm–1; this is superior to 45 nm silicon technology node transistors in terms of size and electronic performance. Six nanotube FETs are used to create a static random-access memory cell with an area of 0.976 μm2, which is comparable with the 90 nm silicon technology node. A full-contact structure is then introduced between the metal and nanotubes to achieve a low contact resistance of 90 Ω μm and reduce the dependence on the contact length. This is used to create nanotube FETs with a contacted gate pitch of 55 nm—corresponding to the 10 nm node—with carrier mobility and Fermi velocity higher than the 10 nm silicon metal–oxide–semiconductor transistors.
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The data that support the plots within this paper are available from the corresponding authors upon reasonable request.
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Acknowledgements
This work is supported by the National Key Research & Development Program (grant no. 2022YFB4401601), Natural Science Foundation of China (62225101), Beijing Municipal Science and Technology Commission (grant no. Z191100007019001-3) and Peking Nanofab Laboratory.
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Z.Z. and L.-M.P. proposed and supervised the project. Y.L. and Y.C. fabricated the scaled aligned CNT FETs and 6T SRAM cells. Y.L. and Y.C. characterized the devices and 6T SRAM cells. P.Z. calculated the power consumptions of the per write operation between aligned CNT and Si 6T SRAM cells. L.X. extracted the mobility and injection velocity of the CNTs using the virtual source model. S.D. and C.J. performed the TEM characterizations. C.L. and Q.H. helped characterize the devices. Y.L., Y.C., Z.Z. and L.-M.P. analysed the data and wrote the manuscript. All authors discussed the results and commented on the manuscript.
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Lin, Y., Cao, Y., Ding, S. et al. Scaling aligned carbon nanotube transistors to a sub-10 nm node. Nat Electron 6, 506–515 (2023). https://doi.org/10.1038/s41928-023-00983-3
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DOI: https://doi.org/10.1038/s41928-023-00983-3
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