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Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform

Nature Nanotechnology volume 18, pages 456–463 (2023)Cite this article

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Abstract

Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS2) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal–oxide–semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal–organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm2 V−1 s−1. Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics.

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Fig. 1: Low-temperature MOCVD of MoS2.
Fig. 2: Material characterization.
Fig. 3: Uniformity characterization of the 200 mm monolayer MoS2 synthesized at low temperature.
Fig. 4: BEOL integration of MoS2 transistors with silicon transistors.

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Data availability

All data are available in the paper and Supplementary Information. All materials are available on figshare at https://doi.org/10.6084/m9.figshare.21761057 or upon request from T.P.

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Acknowledgements

We thank C. Lin and A. Zubair for helpful discussions. We are also grateful for the assistance from Y. Shao, J.-H. Hsia, A. Yao, Y. Yang, A. Penn, D. Morales, Y. Hou, J. Moodera, J. Baylon, P. Kingsview, M. Hempel, G. Riggott and K. Broderick. This work was carried out in part through the use of MIT.nano’s facilities and with the support of the TSMC University Shuttle Program. J.Z., M.X. and T.P. are supported by the MIT-Army Institute for Soldier Nanotechnologies (W911NF-13-D-0001), the NSF Center for Integrated Quantum Materials (grant DMR-1231319) and Ericsson AB. J.-H.P., J.W., Z.W. and J.K. acknowledge the support from the US Army Research Office MURI project under grant number W911NF-18-1-04320432 and the US Army Research Office through the Institute for Soldier Nanotechnologies at MIT, under cooperative agreement number W911NF-18-2-0048. T.Z. and X.Z. acknowledge the support from the US Department of Energy (DOE), Office of Science, Basic Energy Sciences under award DE-SC0020042. For authors from the MIT Lincoln Laboratory (S.A.V. and M.M.), this work is approved for public release. Distribution is unlimited. This material is based upon work supported by the Under Secretary of Defense for Research and Engineering under Air Force contract number FA8702-15-D-0001. Any opinions, findings, conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the Under Secretary of Defense for Research and Engineering. W.G. and G.S.J. acknowledge support by the Laboratory Directed Research and Development Program of Oak Ridge National Laboratory, managed by UT–Battelle, LLC, for the US DOE under contract DE-AC05-00OR22725 (Eugene P. Wigner Fellowship). This research used resources from the Compute and Data Environment for Science at the Oak Ridge National Laboratory, which is supported by the Office of Science of the US DOE under contract number DE-AC05-00OR22725. This manuscript has been authored by UT–Battelle, LLC, under contract number DE-AC05-00OR22725 with the US DOE. The United States Government retains and the publisher, by accepting the article for publication, acknowledges that the United States Government retains a non-exclusive, paid-up, irrevocable, world-wide license to publish or reproduce the published form of this manuscript, or allow others to do so, for United States Government purposes. The US DOE will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan (http://energy.gov/downloads/doe-public-access-plan). M.A. acknowledges the support from the MITRE Innovation Program, the NSF Graduate Research Fellowship Program (grant 1745302) and the MathWorks Engineering Fellowship. J.H. is supported by Ericsson AB. A.C. acknowledges the support from the MITRE Innovation Program and Ericsson AB.

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Author notes

  1. These authors contributed equally: Jiadi Zhu, Ji-Hoon Park.

Authors and Affiliations

  1. Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA

    Jiadi Zhu, Ji-Hoon Park, Jiangtao Wang, Tianyi Zhang, Maitreyi Ashok, Mantian Xue, Xudong Zheng, Zhien Wang, Anantha P. Chandrakasan, Jing Kong & Tomás Palacios

  2. Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, MA, USA

    Steven A. Vitale & Mohamed Mohamed

  3. Computational Sciences and Engineering Division, Oak Ridge National Laboratory, Oak Ridge, TN, USA

    Wenjun Ge & Gang Seob Jung

  4. Ericsson Research, Ericsson AB, Gothenburg, Sweden

    Jonas Hansryd

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Contributions

T.P. and J.K. supervised the project. J.Z., T.P. and J.-H.P. conceived the experiments. J.Z. and J.-H.P. performed the material synthesis. J.-H.P., T.Z. and Z.W. performed the material characterizations. J.Z. and J.-H.P. fabricated the MoS2 transistors. J.-H.P., J.Z. and J.W. designed the MOCVD system. J.Z., J.-H.P. and M.X. carried out the device measurements. S.A.V. and M.M. fabricated the silicon transistors and circuits. W.G. and G.S.J. designed the CFD models and contributed equally to the simulations. J.W. helped with the initial fluid dynamics simulations. M.A. carried out the ADC design and measurements. M.X., X.Z., J.H., A.C. and J.K. participated in data analysis. J.Z. wrote the paper. All authors read and revised the paper.

Corresponding authors

Correspondence to Jing Kong or Tomás Palacios.

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Competing interests

J.Z., J.-H.P., J.W., J.K. and T.P. have applied for a provisional patent (application number, 63/398,331; filing date, 16 August 2022) related to the results presented in Figs. 1–4 and Extended Data Figs. 2,3,5–7. Formal patent pending. The other authors declare no competing interests.

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Extended data

Extended Data Fig. 1 Detailed Photographs of the custom MOCVD system.

a, Overview of the MOCVD system. From left to right are: 1) Controlling computer, 2) Mass flow controllers, precursors and gas inlet, 3) Reaction chamber, 4) Dry pump and vacuum gauge, 5) Stainless steel enclosure. b, 8-inch quartz wafer boat. To avoid potential blocking of the gas flow by the quartz wafer boat, we cut away the parts in the red rectangle. c, Picture of an 8” wafer vertically mounted to the adapted 8-inch quartz wafer boat. There is no blocking on the front side to ensure uniform MoS2 growth on the wafer. The dark color on the quartz wafer boat comes from the MoS2 accumulated during the deposition process.

Extended Data Fig. 2 MOCVD synthesis process of monolayer MoS2 film.

a, SEM image of MoS2 synthesized after 40 mins. b, SEM image of MoS2 synthesized after 55 mins. c, SEM image of MoS2 synthesized after 60 mins. The discrete flakes gradually merge into a continuous film with grain size around 200 nm. scale bar: 1 µm. d, Selective area electron diffraction (SAED) pattern of the synthesized monolayer MoS2 thin film, a polycrystalline structure can be observed. e, HR-STEM image of a region where two grains with different crystal orientation are merged. Good stitching between the grains can be observed. f, Fast Fourier transform (FFT) of (e). Two different set of single crystal MoS2 patterns are overlaid together. g, FFT of the region in the orange rectangle in (e), where two grains merged together. Two sets of single crystal MoS2 patterns can be observed. h, FFT of the region in the red rectangle in (e). Single crystal MoS2 pattern can be observed. i, FFT of the region in the green rectangle in (e). Single crystal MoS2 pattern can be observed. j, Raman spectrum of MOCVD-grown MoS2 under low growth temperature (~275 °C).

Extended Data Fig. 3 Supplementary data for wafer scale uniformity.

a, Optical image of one back-gate MoS2 transistor on Al2O3/Si substrate. b, Hysteresis measurement of one of the MoS2 transistors with PMMA passivation. The gate voltage was swept from −2 V to 7 V (blue curve), and from 7 V to −2 V (red curve). The sweep speed is around 55 mV/sec with VDS = 0.7 V. The measurement was carried out in dark and ambient condition. c, Peak position mapping of the photoluminescence (PL) data over the 8-inch wafer. d, Integrated intensity mapping of the PL data over the 8-inch wafer. The color represents the integrated intensity of the peak from 1.82 eV to 1.90 eV photon energy. 100% refers to the highest integrated intensity of the monolayer MoS2 thin film measured over the 8-inch wafer. e, Optical image of the 8-inch wafer with fabricated MoS2 transistors. 300 nm SiO2/Si substrate was used as the global back gate structure. f, On-state resistance mapping of back-gated MoS2 transistors over 8-inch wafer. g, 4 MoS2 transistors which can represent the typical performance of transistors in the center region on 4 different 8” wafers.

Extended Data Fig. 4 Probability distribution functions (device counts) associated with the mapping data in Fig. 3 and Extended Data Fig. 3.

The red lines demonstrate the fitted Gaussian function based on the probability distribution. a, Peak position of photoluminescence (PL) measurement, b, Full width at half maximum (FWHM) of PL measurement, c, Integrated PL intensity. The gaussian fitting does not apply to this figure. d, Intensity of Raman A1g peak. e, FWHM of Raman \({\mathrm{E}}_{2{\mathrm{g}}}^1\) peak. f, mobility extracted from “Y-function” method. g, Threshold voltage. h, minimum subthreshold swing extracted from transfer characteristics. i, On-state resistance. The Gaussian fitting does not apply to this figure as it is impacted by multiple factors, for example contact resistance, channel resistance, fabrication variations, etc.

Extended Data Fig. 5 Feasibility of BEOL integration with MoS2 on top of silicon.

a, Sulfurization of aluminum wires inside MOCVD chamber during the MoS2 growth process. Even at temperatures as low as 190 °C, the sulfurization of aluminum wires still takes place, generating insulating aluminum sulfides which degrade the conductivity of the aluminum wire. b, SEM image of the as-fabricated silicon transistors (top-layer metal). c, SEM image of the silicon transistor after atomic layer deposition (ALD) passivation of 20 nm Al2O3. d, SEM image of the silicon transistor after MOCVD MoS2 growth. e, SEM image of the MoS2 flakes grown on the silicon CMOS sample (with 20 nm Al2O3 passivation) after 40 mins. The dark triangle-like flakes are monolayer MoS2 before coalescence. The squares are dummy top layer metals for the FEOL silicon circuits. f, resistance change of aluminum wires with and without Al2O3 passivation. g, resistance change of aluminum wires with SiO2 passivation (different thickness) and without passivation.

Extended Data Fig. 6 BEOL integration of MoS2 transistors with silicon transistors.

a, Transfer and b, output characteristics of the as-fabricated silicon devices (black curves) and after: ALD passivation of 20 nm Al2O3 (blue curves), MOCVD growth of monolayer MoS2 (red curves), and BEOL integration (green curves). c, MoS2 transistors with finger source/drain structures on silicon CMOS circuits before the top gate dielectric and gate terminal is formed. d-i, repeated measurements on one pMOSFET and one nMOSFET without the ALD and the MOCVD process to show the cycle-to-cycle variation caused by device measurements. d, Transfer characteristics of one silicon pMOSFET and one silicon nMOSFET during 10 consecutive measurements. e, Output characteristics of one silicon pMOSFET and one silicon nMOSFET during 10 consecutive measurements. f, Threshold voltage distribution of the silicon pMOSFET during the 10 measurements. g, Threshold voltage distribution of the silicon nMOSFET during the 10 measurements. h, On-current distribution of the silicon pMOSFET during the 10 measurements. i, On-current distribution of the silicon nMOSFET during the 10 measurements.

Extended Data Fig. 7 MoS2 growth on top of a foundry fabricated 8-bit analog-digital converter (ADC).

a, 8-bit ADC performance before MOCVD growth. Sine wave with 1.07 V amplitude, 15 kHz frequency was used as the input signal. 10 digital output waveforms are collected and plotted. b, 8-bit ADC performance after the MOCVD growth. Same input signal is used. The output digital signals demonstrate same performance as the pre-grown samples. c-e, Comparison of the (c) lowest digital output, (d) highest digital output, and (e) total digital output range before (grey bars) and after (green bars) the MOCVD growth.

Supplementary information

Supplementary Information

Supplementary Notes 1–7, Figs. 1–11 and Tables 1 and 2.

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Zhu, J., Park, JH., Vitale, S.A. et al. Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform. Nat. Nanotechnol. 18, 456–463 (2023). https://doi.org/10.1038/s41565-023-01375-6

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