Designing a monolithic 3D structure with interleaved logic and high-density memory layers has been difficult to achieve due to challenges in managing the thermal budget. Here, the authors demonstrate a 3D integration of monolayer MoS2 transistors with 3D vertical RRAMs through a low-temperature fabrication process whose 1T–nR structure shows high promise for low-power and high-density memory applications.
- Maosong Xie
- Yueyang Jia
- Rui Yang