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3D Integrated Circuits and Heterogeneous Integration
Submission status
Open
Submission deadline
3D integrated circuits promise smaller, faster devices with lower power consumption. Vertically stacked 3D integrated circuits also enable novel in-memory and in-sensor computing paradigms and incorporate functionally diverse materials, which can benefit many edge applications. There are several complementary approaches to 3D integration. For example, 3D heterogeneous integration involves stacking and interconnecting multiple chips, each potentially made from different materials or optimized for different functions, within a single package. On the other hand, 3D monolithic integration refers to fabricating layers of transistors sequentially on a single wafer, creating a more seamless and compact structure. This approach offers even greater density and performance benefits by reducing interlayer distances and improving signal integrity. Both techniques are crucial for advancing the next generation of high-performance, energy-efficient electronic devices and require interdisciplinary collaborations across materials science, electrical engineering, and semiconductor manufacturing.
In this Communications Engineering collection, we aim to drive research in the engineering side of 3D integration by bringing together the following topics of interest:
Novel materials for 3D integration including 2D materials, oxide semiconductors, etc.
Novel fabrication techniques for 3D integration
Innovation in devices for 3D integration including memory devices, compute elements, and sensors
CMOS-compatibility and BEOL integration approaches
VLSI circuits and architectures for 3D integration
Applications for 3D ICs including edge computing and sensing
Kyoung Yeon Kim and colleagues report the importance of quantum geometrical effects that serve as a bottleneck in stacked nanosheet GAAFETs. This highlights that full quantum mechanics-based device design is crucial for realizing ideal carrier injection characteristics in future technology nodes.
Dr Roland Brunner and colleagues demonstrate how acoustic interferometry can be used to conduct a non-destructive and high-resolution failure analysis of through-silicon vias. They analyse the detection of nanometre-scale cracks and discuss how the opening angle of the acoustic lens impacts on performance.
Hyun Kum and colleagues report on the heterogeneous integration of high-k single-crystalline strontium titanium oxide within gallium nitride high-electron-mobility transistors. As the dielectric material is epitaxially grown and transferred, they achieve low defect density between the gate oxide and transistor heterostructures.
Gate-all-round field effect transistors (FETs) with channels fabricated from highly stacked nanowires can enhance the drive current of such devices for a fixed footprint. Chen, Liu, and colleagues fabricated FETs with as many as 16 highly stacked Ge0.95Si0.05 nanowires and 12 nanowires without parasitic channels using wet etching.